Built-in Self-test Preparation in Fpgas

This paper addresses the problem of Test Effectiveness (TE) evaluation of a FPGA BIST solution, through Hardware Fault Simulation (HFS). A novel HFS technique is proposed, that efficiently, using partial reconfiguration, ascertain (or not) the BIST. The proposed methodology can be particularly useful for signature fault dictionary building and for applications in which multiple fault injection is mandatory. HFS is performed using local partial reconfiguration with small binary files. The limitation of injecting faults in Look-Up Tables (LUTs) is evaluated as a sampling technique. The methodology is fully automated and our results show that it can be orders of magnitude faster than software or fully reconfigurable hardware fault simulation.